1. Field of the Invention
This invention relates to the field of circuit cell libraries as used, for example, in the design of integrated circuits. More particularly, this invention relates to the characterizing of performance parameter variability in response to perturbations in manufacturing process parameters for circuit cells within a library of circuit cells.
2. Description of the Prior Art
It is known to provide libraries of circuit cell designs from which complex integrated circuits can be formed. The circuit cells can comprise primitive circuit elements, such as AND gates and OR gates, as well as more complicated circuit cells having more sophisticated functionality. These circuit cell libraries typically specify at a physical level how the circuit of the circuit cell concerned should be formed, e.g. the topology of the semiconductor, metal and other layers forming the circuit cell, the dimensions of such layers, the chemical compositions of such layers and the like. Electronic design automation (EDA) software tools use such circuit cell libraries as one input together with a higher level specification of an integrated circuit design (such as a register transfer language (RTL) file logically defining the integrated circuit) and use these inputs to generate data defining the masks and other required low-level design information needed for the manufacturing process.
An increasingly important aspect of the above methodology is the effect that manufacturing process perturbations can have upon the integrated circuit performance and the yield of correctly operating integrated circuits. A circuit cell library may specify particular nominal design parameters, e.g. dimensions, dopant levels etc, but when the integrated circuit is manufactured there will be some tolerance within which the manufacturing process is able to meet these design parameters, e.g. a layer thickness will vary from the design thickness by a certain amount in accordance with normal statistical variation. As process size diminishes and performance of integrated circuits increases, the tolerances within which the circuit cells can be manufactured and the effect that this has upon the performance parameters of those circuit cells becomes larger and more significant. This can lead to reductions in the performance that can be achieved and reductions in the yield of correctly functioning integrated circuits. As an example, an integrated circuit may contain several critical paths through which a signal must propagate within a certain time if the integrated circuit is to operate correctly. If all of the circuit cells are manufactured exactly to their design specification, then this critical path may be met. However, perturbations within the manufacturing process parameters can adversely affect the signal propagation speed through circuit cells and have the result that critical path timing is no longer met. In order to reduce the adverse effect of such process variations it is known to evaluate how process variations will affect circuit performance using EDA tools. In this way, portions of a design which are too sensitive to process variations can be altered in order to give more margin for manufacturing variations and to permit increased performance to be achieved and/or to increase the manufacturing yield.
In order to model the effect of manufacturing process variation upon performance parameters of circuit cells, it is known to provide data representing these variations. FIG. 1 of the accompanying drawings schematically illustrates a circuit cell in the form of NAND gate 2 which when manufactured exactly in accordance with its design parameters have a nominal delay for signal propagation therethrough given by Dnom. When the circuit cell library is being formed, gate level modeling of the circuit cell 2 using, for example, SPICE models is performed to investigate how the delay through the circuit cell 2 varies with changes in the manufacturing process parameters. At an abstract level, the manufacturing process parameters can be considered to be a set of parameters each having nominal values p1, p2, etc. If the circuit cell 2 is manufactured exactly in accordance with these nominal manufacturing process parameters, then the circuit cell 2 will give the expected nominal delay. However, perturbations to these manufacturing process parameters are likely and these perturbations can be considered as Δp1, Δp2 etc. The SPICE model of the circuit cell is evaluated at different values of the respective perturbations Δp1, Δp2 in order to determine coefficients k1, k2, etc associated with each of these perturbations and indicative of how strongly the performance parameter, such as delay, varies with these perturbations.
FIG. 2 of the accompanying drawings illustrates how the perturbed delay D can be formed as the sum of the nominal delay Dnom together with the sum of the changes in the delay produced by each of the perturbations of the respective manufacturing process parameters. This model assumes that the effect of the perturbations of different manufacturing process parameters are independent of one another. This is not always true and results in error within this technique.
A typical circuit cell library will comprise many hundreds of circuit cell designs. When seeking to characterise the nominal performance and the variation in the nominal performance with respect of variations in manufacturing process parameters, SPICE modeling has to be performed in respect of the full set of circuit cells for each process point being investigated. Thus, when attempting to identify the coefficients k1, k2, etc even on the basis of a crude approximation such as sampling one point above the nominal manufacturing process parameter, the nominal process parameter and one point below the nominal process parameter, if there are n circuit cells within the library, this will require the modeling of 2n+1 circuit cell libraries. This large quantity of modeling needed represents a disadvantageous burden upon the generation of appropriately characterised circuit cell libraries.